PIC18LF24K Datasheet, PDF (162/594 Pages) –

PIC18(L)F26/45/46K40
13.9 Program Memory Scan
Configuration
If desired, the program memory scan module may be
used in conjunction with the CRC module to perform a
CRC calculation over a range of program memory
addresses. In order to set up the scanner to work with
the CRC you need to perform the following steps:
1. Set the Enable bit in both the CRCCON0 and
SCANCON0 registers. If they get disabled, all
internal states of the scanner and the CRC are
reset (registers are unaffected).
2. Choose which memory access mode is to be
used (see Section 13.11 “Scanning Modes”)
and set the MODE bits of the SCANCON0
register appropriately.
3. Based on the memory access mode, set the
INTM bits of the SCANCON0 register to the
appropriate interrupt mode (see Section
13.11.5 “Interrupt Interaction”)
4. Set the SCANLADRL/H/U and SCANHADRL/H/
U registers with the beginning and ending
locations in memory that are to be scanned.
5. The CRCGO bit must be set before setting the
SCANGO bit. Setting the SCANGO bit starts the
scan. Both CRCEN and CRCGO bits must be
enabled to use the scanner. When either of
these bits are disabled, the scan aborts and the
INVALID bit SCANCON0 is set. The scanner will
wait for the signal from the CRC that it is ready
for the first Flash memory location, then begin
loading data into the CRC. It will continue to do
so until it either hits the configured end address
or an address that is unimplemented on the
device, at which point the SCANGO bit will clear,
Scanner functions will cease, and the SCANIF
interrupt will be triggered. Alternately, the
SCANGO bit can be cleared in software if
desired.
13.10 Scanner Interrupt
The scanner will trigger an interrupt when the
SCANGO bit transitions from ‘1’ to ‘0’. The SCANIF
interrupt flag of PIR7 is set when the last memory
location is reached and the data is entered into the
CRCDATA registers. The SCANIF bit can only be
cleared in software. The SCAN interrupt enable is the
SCANIE bit of the PIE7 register.
13.11 Scanning Modes
The memory scanner can scan in four modes: Burst,
Peek, Concurrent, and Triggered. These modes are
controlled by the MODE bits of the SCANCON0
register. The four modes are summarized in Table 13-2.
13.11.1 BURST MODE
When MODE = 01, the scanner is in Burst mode. In
Burst mode, CPU operation is stalled beginning with the
operation after the one that sets the SCANGO bit, and
the scan begins, using the instruction clock to execute.
The CPU is held in its current state until the scan stops.
Note that because the CPU is not executing instructions,
the SCANGO bit cannot be cleared in software, so the
CPU will remain stalled until one of the hardware end-
conditions occurs. Burst mode has the highest
throughput for the scanner, but has the cost of stalling
other execution while it occurs.
13.11.2 CONCURRENT MODE
When MODE = 00, the scanner is in Concurrent mode.
Concurrent mode, like Burst mode, stalls the CPU
while performing accesses of memory. However, while
Burst mode stalls until all accesses are complete,
Concurrent mode allows the CPU to execute in
between access cycles.
13.11.3 TRIGGERED MODE
When MODE = 11, the scanner is in Triggered mode.
Triggered mode behaves identically to Concurrent
mode, except instead of beginning the scan
immediately upon the SCANGO bit being set, it waits
for a rising edge from a separate trigger clock, the
source of which is determined by the SCANTRIG
register.
13.11.4 PEEK MODE
When MODE = 10, the scanner is in Peek mode. Peek
mode waits for an instruction cycle in which the CPU
does not need to access the NVM (such as a branch
instruction) and uses that cycle to do its own NVM
access. This results in the lowest throughput for the NVM
access (and can take a much longer time to complete a
scan than the other modes), but does so without any
impact on execution times, unlike the other modes.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 162