PIC18LF24K Datasheet, PDF (189/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 14-21: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
RC2IP
TX2IP
RC1IP
TX1IP
BCL2IP
SSP2IP
bit 7
R/W-1/1
BCL1IP
R/W-1/1
SSP1IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RC2IP: EUSART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
TX2IP: EUSART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: EUSART1 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: EUSART1 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
BCL2IP: MSSP2 Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
SSP2IP: Synchronous Serial Port 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
BCL1IP: MSSP1 Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
SSP1IP: Synchronous Serial Port 1 Interrupt Priority bit
1 = High priority
0 = Low priority
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 189