PIC18LF24K Datasheet, PDF (58/594 Pages) –

PIC18(L)F26/45/46K40
6.0 POWER-SAVING OPERATION
MODES
The purpose of the Power-Down modes is to reduce
power consumption. There are three Power-Down
modes:
• Doze mode
• Sleep mode
• Idle mode
6.1 Doze Mode
Doze mode allows for power saving by reducing CPU
operation and program memory (PFM) access, without
affecting peripheral operation. Doze mode differs from
Sleep mode because the bandgap and system
oscillators continue to operate, while only the CPU and
PFM are affected. The reduced execution saves power
by eliminating unnecessary operations within the CPU
and memory.
When the Doze Enable (DOZEN) bit is set
(DOZEN = 1), the CPU executes only one instruction
cycle out of every N cycles as defined by the
DOZE<2:0> bits of the CPUDOZE register. For
example, if DOZE<2:0> = 001, the instruction cycle
ratio is 1:4. The CPU and memory execute for one
instruction cycle and then lay idle for three instruction
cycles. During the unused cycles, the peripherals
continue to operate at the system clock speed.
6.1.1 DOZE OPERATION
The Doze operation is illustrated in Figure 6-1. For this
example:
• Doze enable (DOZEN) bit set (DOZEN = 1)
• DOZE<2:0> = 001 (1:4) ratio
• Recover-on-Interrupt (ROI) bit set (ROI = 1)
As with normal operation, the PFM fetches for the next
instruction cycle. The Q-clocks to the peripherals
continue throughout.
FIGURE 6-1:
System
Clock
DOZE MODE OPERATION EXAMPLE (DOZE<2:0> = 001, 1:4)
1
1
1
1
1
1
1
1
1
1
1
1
1
/ŶƐƚƌƵĐƚŝŽŶ
WĞƌŝŽĚ
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
CPU Clock
PFM Op’s
1234
Fetch
1234
Fetch
12341234123412341234
Push
0004h
Fetch
Fetch
CPU Op’s
Exec
Exec
Exec^(1,2)
NOP
Exec
Exec
Exec
I nter rup t
Here
(ROI = 1)
Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.
2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 58