PIC18LF24K Datasheet, PDF (378/594 Pages) –

PIC18(L)F26/45/46K40
26.10.8 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPxCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCL pin is deasserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode
(Figure 26-30).
26.10.8.1 WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
26.10.9 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPxCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPxSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 26-31).
26.10.9.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 26-30: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPxCON2
ACKEN = 1, ACKDT = 0
SDA
D0
TBRG
TBRG
ACK
ACKEN automatically cleared
SCL
8
9
SSPxIF
SSPxIF set at
the end of receive
Cleared in
software
Note: TBRG = one Baud Rate Generator period.
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
FIGURE 26-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPxCON2,
set PEN
Falling edge of
9th clock
SCL
TBRG
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPxSTAT<4>) is set.
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
SDA
ACK
TBRG
TBRG
P
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 378