PIC18LF24K Datasheet, PDF (228/594 Pages) –

PIC18(L)F26/45/46K40
19.1 Register Definitions: Timer1/3/5
Long bit name prefixes for the Timer1/3/5 are shown in
Table 20-1. Refer to Section 1.4.2.2 “Long Bit
Names” for more information.
TABLE 19-1:
Peripheral
Bit Name Prefix
Timer1
T1
Timer3
T3
Timer5
T5
REGISTER 19-1: TxCON: TIMERx CONTROL REGISTER
U-0
U-0
R/W-0/u
R/W-0/u
U-0
—
—
CKPS<1:0>
—
bit 7
R/W-0/u
SYNC
R/W-0/0
RD16
R/W-0/u
ON
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
u = unchanged
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
CKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
Unimplemented: Read as ‘0’
SYNC: Timerx External Clock Input Synchronization Control bit
TMRxCLK = FOSC/4 or FOSC:
This bit is ignored. Timer1 uses the incoming clock as is.
Else:
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock
RD16: 16-Bit Read/Write Mode Enable bit
1 = All 16 bits of Timer1 can be read simultaneously (TMR1H is buffered)
0 = 16-bit reads of Timer1 are disabled (TMR1H not buffered)
ON: Timerx On bit
1 = Enables Timerx
0 = Disables Timerx
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 228