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PIC18LF24K Datasheet, PDF (500/594 Pages) – | |||
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PIC18(L)F26/45/46K40
DECFSZ
Decrement f, skip if 0
Syntax:
DECFSZ f {,d {,a}}
Operands:
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
Operation:
(f) â 1 ï® dest,
skip if result = 0
Status Affected:
None
Encoding:
0010 11da ffff ffff
Description:
The contents of register âfâ are
decremented. If âdâ is â0â, the result is
placed in W. If âdâ is â1â, the result is
placed back in register âfâ (default).
If the result is â0â, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a 2-cycle instruction.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank.
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See Sec-
tion 35.2.3 âByte-Oriented and Bit-
Oriented Instructions in Indexed Lit-
eral Offset Modeâ for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
If skip:
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
DECFSZ CNT, 1, 1
GOTO
LOOP
CONTINUE
Before Instruction
PC
=
After Instruction
CNT =
If CNT =
PC =
If CNT ï¹
PC =
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
DCFSNZ
Decrement f, skip if not 0
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
Operation:
(f) â 1 ï® dest,
skip if result ï¹ 0
Status Affected:
None
Encoding:
0100 11da ffff ffff
Description:
The contents of register âfâ are
decremented. If âdâ is â0â, the result is
placed in W. If âdâ is â1â, the result is
placed back in register âfâ (default).
If the result is not â0â, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a 2-cycle
instruction.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank.
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See Sec-
tion 35.2.3 âByte-Oriented and Bit-
Oriented Instructions in Indexed Lit-
eral Offset Modeâ for details.
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
If skip:
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
=?
= TEMP â 1,
= 0;
= Address (ZERO)
ï¹ 0;
= Address (NZERO)
ï£ 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 500
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