PIC18LF24K Datasheet, PDF (312/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 24-3: CWG1CLKCON: CWG1 CLOCK INPUT SELECTION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 7
R/W-0/0
CS
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-1
bit 0
Unimplemented: Read as ‘0’
CS: CWG Clock Source Selection Select bits
CS
Clock Source
1
HFINTOSC (remains operating during Sleep)
0
FOSC
REGISTER 24-4: CWG1ISM: CWGx INPUT SELECTION REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
bit 7
R/W-0/0
ISM<2:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-3
bit 2-0
Unimplemented Read as ‘0’
ISM<2:0>: CWG Data Input Selection Multiplexer Select bits
ISM<2:0>
111
110
101
100
011
010
001
000
Input Source
DSM OUT
CMP2 OUT
CMP1 OUT
PWM4 OUT
PWM3 OUT
CCP2 OUT
CCP1 OUT
Pin selected by CWG1PPS
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 312