PIC18LF24K Datasheet, PDF (145/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 11-2: NVMCON2: NONVOLATILE MEMORY CONTROL 2 REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMCON2<7:0>
bit 7
R/W-0
bit 0
Legend:
R = Readable bit
x = Bit is unknown
-n = Value at POR
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
bit 7-0
NVMCON2<7:0>:
Refer to Section 11.1.4 “NVM Unlock Sequence”.
Note 1: This register always reads zeros, regardless of data written.
Register 11-3:
R/W-x/0
bit 7
NVMADRL: Data EEPROM Memory Address Low
R/W-x/0
R/W-x/0
R/W-x/0
R/W-x/0
R/W-x/0
NVMADR<7:0>
R/W-x/0
R/W-x/0
bit 0
Legend:
R = Readable bit
x = Bit is unknown
-n = Value at POR
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
bit 7-0
NVMADR<7:0>: EEPROM Read Address bits
REGISTER 11-4: NVMADRH: DATA EEPROM MEMORY ADDRESS HIGH⁽¹⁾
U-0
U-0
U-0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
—
—
—
—
—
—
NVMADR<9:8>
bit 7
bit 0
Legend:
R = Readable bit
x = Bit is unknown
-n = Value at POR
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
NVMADR<9:8>: EEPROM Read Address bits
Note 1: The NVMADRH register is not implemented on PIC18(L)F45K40.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 145