PIC18LF24K Datasheet, PDF (291/594 Pages) –

PIC18(L)F26/45/46K40
24.0 COMPLEMENTARY
WAVEFORM GENERATOR
(CWG) MODULE
The Complementary Waveform Generator (CWG)
produces half-bridge, full-bridge, and steering of PWM
waveforms. It is backwards compatible with previous
CCP functions. The PIC18(L)F2x/4xK40 family has
one instance of the CWG module.
The CWG has the following features:
• Six operating modes:
- Synchronous Steering mode
- Asynchronous Steering mode
- Full-Bridge mode, Forward
- Full-Bridge mode, Reverse
- Half-Bridge mode
- Push-Pull mode
• Output polarity control
• Output steering
• Independent 6-bit rising and falling event dead-
band timers
- Clocked dead band
- Independent rising and falling dead-band
enables
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart option
- Auto-shutdown pin override control
24.1 Fundamental Operation
The CWG generates two output waveforms from the
selected input source.
The off-to-on transition of each output can be delayed
from the on-to-off transition of the other output, thereby,
creating a time delay immediately where neither output
is driven. This is referred to as dead time and is covered
in Section 24.6 “Dead-Band Control”.
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. This is
referred to as auto-shutdown and is covered in Section
24.10 “Auto-Shutdown”.
24.2 Operating Modes
The CWG module can operate in six different modes,
as specified by the MODE<2:0> bits of the
CWG1CON0 register:
• Half-Bridge mode
• Push-Pull mode
• Asynchronous Steering mode
• Synchronous Steering mode
• Full-Bridge mode, Forward
• Full-Bridge mode, Reverse
All modes accept a single pulse data input, and
provide up to four outputs as described in the following
sections.
All modes include auto-shutdown control as described
in Section 24.10 “Auto-Shutdown”
Note:
Except as noted for Full-bridge mode
(Section 24.2.3 “Full-Bridge Modes”),
mode changes should only be performed
while EN = 0 (Register 24-1).
24.2.1 HALF-BRIDGE MODE
In Half-Bridge mode, two output signals are generated
as true and inverted versions of the input as illustrated
in Figure 24-2. A non-overlap (dead-band) time is
inserted between the two outputs to prevent shoot
through current in various power supply applications.
Dead-band control is described in Section
24.6 “Dead-Band Control”. The output steering fea-
ture cannot be used in this mode. A basic block dia-
gram of this mode is shown in Figure 24-1.
The unused outputs CWG1C and CWG1D drive similar
signals, with polarity independently controlled by the
POLC and POLD bits of the CWG1CON1 register,
respectively.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 291