PIC18LF24K Datasheet, PDF (415/594 Pages) –

PIC18(L)F26/45/46K40
27.5.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 27.5.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCxREG register. If the RCxIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
27.5.2.4 Synchronous Slave Reception
Setup:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for both the CKx and DTx
pins (if applicable).
3. If interrupts are desired, set the RCxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
6. The RCxIF bit will be set when reception is
complete. An interrupt will be generated if the
RCxIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCxSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCxREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 27-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDxCON ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
INTCON
GIE/GIEH PEIE/GIEL IPEN
—
—
INT2EDG INT1EDG INT0EDG
PIE3
RC2IE
TX2IE
RC1IE
TX1IE
BCL2IE SSP2IE BCL1IE SSP1IE
PIR3
RC2IF
TX2IF
RC1IF
TX1IF
BCL2IF SSP2IF BCL1IF SSP1IF
IPR3
RC2IP
TX2IP
RC1IP
TX1IP
BCL2IP SSP2IP BCL1IP SSP1IP
RCxREG
EUSART Receive Data Register
RCxSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RxyPPS
—
—
—
RxyPPS<4:0>
RXxPPS
—
—
—
RXPPS<4:0>
TXxSTA
Legend:
*
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Page provides register information.
Register
on Page
390
169
181
173
189
394*
389
217
215
388
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 415