PIC18LF24K Datasheet, PDF (288/594 Pages) –

PIC18(L)F26/45/46K40
The pull-up and pull-down resistor values are
significantly affected by small variations of VCPINV.
Measuring VCPINV can be difficult, especially when the
waveform is relative to VDD. However, by combining
Equations 23-2 and 23-3, the resistor value can be
determined from the time difference between the
ZCD_output high and low periods. Note that the time
difference, ∆T, is 4*TOFFSET. The equation for
determining the pull-up and pull-down resistor values
from the high and low ZCD_output periods is shown in
Equation 23-4.
EQUATION 23-4: PULL-UP/DOWN
RESISTOR VALUES


R
=
R
SER
I
ES


--------------------------^V----^B---^I--^A---^S--------------------------
–

1


V
P
E
A
K_
sin


F
re
q
_---_--2--T_----




R is pull-up or pull-down resistor.
VBIAS is VPULLUP when R is pull-up or VDD when R
is pull-down.
∆T is the ZCDOUT high and low period difference.
23.6 Handling VPEAK Variations
If the peak amplitude of the external voltage is
expected to vary, the series resistor must be selected
to keep the ZCD current source and sink below the
design maximum range of ± 600 A and above a
reasonable minimum range. A general rule of thumb is
that the maximum peak voltage can be no more than
six times the minimum peak voltage. To ensure that the
maximum current does not exceed ± 600 A and the
minimum is at least ± 100 A, compute the series
resistance as shown in Equation 23-5. The
compensating pull-up for this series resistance can be
determined with Equation 23-3 because the pull-up
value is independent from the peak voltage.
EQUATION 23-5: SERIES R FOR V RANGE
RSERIES
=
-^V----^M----^A---^X---^P---^E---^A---^K----+-----^V----^M----^I--^N---^P---^E---^A---^K--
710^–4
23.7 Operation During Sleep
The ZCD current sources and interrupts are unaffected
by Sleep.
23.8 Effects of a Reset
The ZCD circuit can be configured to default to the active
or inactive state on Power-on-Reset (POR). When the
ZCD Configuration bit is cleared, the ZCD circuit will be
active at POR. When the ZCD Configuration bit is set,
the ZCDSEN bit of the ZCDCON register must be set to
enable the ZCD module.
23.9 Disabling the ZCD Module
The ZCD module can be disabled in two ways:
1. Configuration Word 2H has the ZCD bit which
disables the ZCD module when set, but it can be
enabled using the ZCDSEN bit of the ZCDCON
register (Register 23-1). If the ZCD bit is clear,
the ZCD is always enabled.
2. The ZCD can also be disabled using the
ZCDMD bit of the PMD2 register (Register 7-3).
This is subject to the status of the ZCD bit.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 288