PIC18LF24K Datasheet, PDF (372/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 26-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
BRG
Value
BRG
Reload
DX
DX ‚ – 1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
26.10.3 WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL bit is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not idle.
Note:
Because queuing of events is not allowed,
writing to the lower five bits of SSPxCON2
is disabled until the Start condition is
complete.
26.10.4 I²C MASTER MODE START
CONDITION TIMING
To initiate a Start condition (Figure 26-26), the user
sets the Start Enable bit, SEN bit of the SSPxCON2
register. If the SDA and SCL pins are sampled high,
the Baud Rate Generator is reloaded with the contents
of SSPxADD<7:0> and starts its count. If SCL and
SDA are both sampled high when the Baud Rate Gen-
erator times out (TBRG), the SDA pin is driven low. The
action of the SDA being driven low while SCL is high is
FIGURE 26-26: FIRST START BIT TIMING
the Start condition and causes the S bit of the
SSPxSTAT1 register to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPxADD<7:0> and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
by hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLxIF, is set, the Start condition is
aborted and the I²C module is reset into
its Idle state.
2: The Philips I²C specification states that a
bus collision cannot occur on a Start.
Write to SEN bit occurs here
Set S bit (SSPxSTAT<3>)
SDA = 1,
SCL = 1
TBRG
TBRG
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
Write to SSPxBUF occurs here
SDA
1st bit
2nd bit
SCL
TBRG
S
TBRG
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 372