PIC18LF24K Datasheet, PDF (169/594 Pages) –

PIC18(L)F26/45/46K40
14.8 Register Definitions: Interrupt Control
REGISTER 14-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
U-0
GIE/GIEH PEIE/GIEL
IPEN
—
U-0
R/W-1/1
—
INT2EDG
bit 7
R/W-1/1
INT1EDG
R/W-1/1
INT0EDG
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
GIE/GIEH: Global Interrupt Enable bit
If IPEN = 1:
1 = Enables all unmasked interrupts and cleared by hardware for high-priority interrupts only
0 = Disables all interrupts
If IPEN = 0:
1 = Enables all unmasked interrupts and cleared by hardware for all interrupts
0 = Disables all interrupts
PEIE/GIEL: Peripheral Interrupt Enable bit
If IPEN = 1:
1 = Enables all low-priority interrupts and cleared by hardware for low-priority interrupts only
0 = Disables all low-priority interrupts
If IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts
Unimplemented: Read as ‘0’
INT2EDG: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge of INT2 pin
0 = Interrupt on falling edge of INT2 pin
INT1EDG: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge of INT1 pin
0 = Interrupt on falling edge of INT1 pin
INT0EDG: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge of INT0 pin
0 = Interrupt on falling edge of INT0 pin
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 169