PIC18LF24K Datasheet, PDF (430/594 Pages) –

PIC18(L)F26/45/46K40
31.2 ADC Operation
31.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. A conversion
may be started by any of the following:
• Software setting the ADGO bit of ADCON0 to ‘1’
• An external trigger (selected by Register 31-3)
• A continuous-mode retrigger (see section Sec-
tion 31.5.8 “Continuous Sampling mode”)
.
Note:
The ADGO bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 31.2.7 “ADC Conver-
sion Procedure (Basic Mode)”.
31.2.2 COMPLETION OF A CONVERSION
When any individual conversion is complete, the value
already in ADRES is written into ADPREV (if
ADPSIS = 1) and the new conversion results appear in
ADRES. When the conversion completes, the ADC
module will:
• Clear the ADGO bit (unless the ADCONT bit of
ADCON0 is set)
• Set the ADIF Interrupt Flag bit
• Set the ADMATH bit
• Update ADACC
When ADDSEN = 0 then after every conversion, or
when ADDSEN = 1 then after every other conversion,
the following events occur:
• ADERR is calculated
• ADTIF is set if ADERR calculation meets thresh-
old comparison
Importantly, filter and threshold computations occur
after the conversion itself is complete. As such,
interrupt handlers responding to ADIF should check
ADTIF before reading filter and threshold results.
31.2.3 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the ADGO bit can be cleared in software. The ADRESH
and ADRESL registers will be updated with the partially
complete Analog-to-Digital conversion sample.
Incomplete bits will match the last bit converted. In this
case, filter and/or threshold occur.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
31.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC oscillator source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
31.2.5
EXTERNAL TRIGGER DURING
SLEEP
If the external trigger is received during sleep while
ADC clock source is set to the FRC, ADC module will
perform the conversion and set the ADIF bit upon com-
pletion.
If an external trigger is received when the ADC clock
source is something other than FRC, the trigger will be
recorded, but the conversion will not begin until the
device exits Sleep.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 430