PIC18LF24K Datasheet, PDF (445/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 31-3: ADCON2: ADC CONTROL REGISTER 2
R/W-0/0
ADPSIS
bit 7
R/W-0/0
R/W-0/0
ADCRS<2:0>
R/W-0/0
R/W/HC-0
ADACLR
R/W-0/0
R/W-0/0
ADMD<2:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6-4
bit 3
bit 2-0
Note 1:
2:
3:
4:
ADPSIS: ADC Previous Sample Input Select bits
1 = ADFLTR is transfered to ADPREV at start-of-conversion
0 = ADRES is transfered to ADPREV at start-of-conversion
ADCRS<2:0>: ADC Accumulated Calculation Right Shift Select bits
If ADMD = 100:
Low-pass filter time constant is 2^ADCRS, filter gain is 1:1
If ADMD = 001, 010 or 011:
The accumulated value is right-shifted by ADCRS (divided by 2^ADCRS)^(1,2)
Otherwise:
Bits are ignored
ADACLR: A/D Accumulator Clear Command bit⁽³⁾
0 = Clearing action is complete (or not started)
1 = ADACC, ADAOV and ADCNT registers are cleared
ADMD<2:0>: ADC Operating Mode Selection bits⁽⁴⁾
111-101 = Reserved
100 = Low-pass Filter mode
011 = Burst Average mode
010 = Average mode
001 = Accumulate mode
000 = Basic (Legacy) mode
To correctly calculate an average, the number of samples (set in ADRPT) must be 2ADCRS.
ADCRS = 3'b111 is a reserved option.
This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator
selections, the delay may be many instructions.
See Table 31-2 for Full mode descriptions.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 445