PIC18LF24K Datasheet, PDF (240/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 19-7:
TMRxGE
TxGPOL
TxGSPM
TxGTM
TxGGO/
DONE
TxG_IN
TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
Set by software
Counting enabled on
rising edge of TxG
Cleared by hardware on
falling edge of TxGVAL
TxCKI
TxGVAL
TIMER1/3/5
N
TMRxGIF
Cleared by software
N+1 N+2 N+3 N+4
Set by hardware on
falling edge of TxGVAL
Cleared by
software
19.13 Peripheral Module Disable
When a peripheral module is not used or inactive, the
module can be disabled by setting the Module Disable
bit in the PMD registers. This will reduce power
consumption to an absolute minimum. Setting the PMD
bits holds the module in Reset and disconnects the
module’s clock source. The Module Disable bits for
Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5
(TMR5MD) are in the PMD1 register. See Section
7.0 “Peripheral Module Disable (PMD)” for more
information.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 240