PIC18LF24K Datasheet, PDF (130/594 Pages) –

PIC18(L)F26/45/46K40
11.1.4 NVM UNLOCK SEQUENCE
The unlock sequence is a mechanism that protects the
NVM from unintended self-write programming or
erasing. The sequence must be executed and
completed without interruption to successfully
complete any of the following operations:
• PFM Row Erase
• Write of PFM write latches to PFM memory
• Write of PFM write latches to User IDs
• Write to Data EEPROM Memory
• Write to Configuration Words
The unlock sequence consists of the following steps
and must be completed in order:
• Write 55h to NVMCON2
• Write AAh to NMVCON2
• Set the WR bit of NVMCON1
Once the WR bit is set, the processor will stall internal
operations until the operation is complete and then
resume with the next instruction.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
FIGURE 11-6:
NVM UNLOCK
SEQUENCE FLOWCHART
Start Unlock Sequence
Write 55h to NVMCON2
Write AAh to NVMCON2
Initiate Write or Erase Operation
(WR = 1)
End Unlock Operation
EXAMPLE 11-2:
BCF
BANKSEL
BSF
MOVLW
NVM UNLOCK SEQUENCE
INTCON,GIE
NVMCON1
NVMCON1,WREN
55h
; Recommended so sequence is not interrupted
; Enable write/erase
; Load 55h
MOVWF
MOVLW
MOVWF
BSF
NVMCON2
AAh
NVMCON2
INTCON1,WR
; Step 1: Load 55h into NVMCON2
; Step 2: Load W with AAh
; Step 3: Load AAh into NVMCON2
; Step 4: Set WR bit to begin write/erase
BSF
INTCON,GIE
; Re-enable interrupts
Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order
shown. If the timing of the steps 1 to 4 is corrupted by an interrupt or a debugger Halt, the action
will not take place.
2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 130