PIC18LF24K Datasheet, PDF (251/594 Pages) –

PIC18(L)F26/45/46K40
20.4 Timer2 Output
The Timer2 module’s primary output is TMR2_posts-
caled, which pulses for a single TMR2_clk period upon
each match of the postscaler counter and the
OUTPS<3:0> bits of the T2CON register. The PR2
postscaler is incremented each time the TMR2 value
matches the PR2 value. This signal can be selected as
an input to several other input modules:
• The CRC memory scanner, as a trigger for
triggered mode
• The ADC module, as an auto-conversion trigger
• Gate source for Timer1/3/5
• CWG, as an auto-shutdown source
• Alternate SPI clock
• Reset signals for other instances of itself
(Timer2/4/6)
In addition, the Timer2 is also used by the CCP module
for pulse generation in PWM mode. Both the actual
TMR2 value as well as other internal signals are sent to
the CCP module to properly clock both the period and
pulse width of the PWM signal. See Section
21.5 “PWM
Overview”
and
Section
22.0 “Pulse-Width Modulation (PWM )” for more
details on setting up Timer2 for use with the CCP and
PWM.
20.5 External Reset Sources
In addition to the clock source, Timer2 also takes in an
external Reset source. This external Reset source is
selected for Timer2, Timer4 and Timer6 with the
T2RST, T4RST and T6RST registers, respectively.
This source can control the starting and stopping of the
timer, as well as resetting the timer, depending on
which mode the timer is in. The mode of the timer is
controlled by the MODE<4:0> bits of the TxHLT
register.
20.5.1 ONE-SHOT MODE
The MODE<3> bit of the TxHLT register controls
whether the timer is in either the One-Shot mode or the
original Normal Period mode. When this bit is set, the
timer acts in the One-Shot mode, meaning that upon
the timer register matching the PRx period register, the
timer will stop incrementing until the timer is manually
started again.
20.6 Operation Examples
Unless otherwise specified, the following notes apply to
the following timing diagrams:
- Both the prescaler and postscaler are set to
1:1 (both the CKPS and OUTPS bits in the
TxCON register are cleared).
- The diagrams illustrate any clock except
FOSC/4 and show clock-sync delays of at
least two full cycles for both ON and
Timer2_ers. When using FOSC/4, the
clock-sync delay is at least one instruction
period for Timer2_ers; ON applies in the next
instruction period.
- ON and Timer2_ers are somewhat general-
ized, and clock-sync delays may produce
results that are slightly different than illus-
trated.
- The PWM Duty Cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module as
described in Section 21.5 “PWM Overview”
and Section 22.0 “Pulse-Width Modula-
tion (PWM )”. The signals are not a part of
the Timer2 module.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 251