PIC18LF24K Datasheet, PDF (441/594 Pages) –

PIC18(L)F26/45/46K40
31.5.1 DIGITAL FILTER/AVERAGE
The digital filter/average module consists of an accu-
mulator with data feedback options, and control logic to
determine when threshold tests need to be applied.
The accumulator is a 16-bit wide register which can be
accessed through the ADACCH:ADACCL register pair.
Upon each trigger event (the ADGO bit set or external
event trigger), the ADC conversion result is added to
the accumulator. If the accumulated value exceeds
2^{(accumulator_width)}-1 = 2¹⁶ = 65535, the overflow bit
ADAOV in the ADSTAT register is set.
The number of samples to be accumulated is
determined by the ADRPT (A/D Repeat Setting)
register. Each time a sample is added to the
accumulator, the ADCNT register is incremented. Once
ADRPT samples are accumulated (ADCNT = ADRPT),
an accumulator clear command can be issued by the
software by setting the ADACLR bit in the ADCON2
register. Setting the ADACLR bit will also clear the
ADAOV (Accumulator overflow) bit in the ADSTAT
register, as well as the ADCNT register. The ADACLR
bit is cleared by the hardware when accumulator
clearing action is complete.
Note:
When ADC is operating from FRC, five
FRC clock cycles are required to execute
the ADACC clearing operation.
The ADCRS <2:0> bits in the ADCON2 register control
the data shift on the accumulator result, which
effectively divides the value in accumulator
(ADACCH:ADACCL) register pair. For the Accumulate
mode of the digital filter, the shift provides a simple
scaling operation. For the Average/Burst Average
mode, the shift bits are used to determine number of
samples for averaging. For the Low-pass Filter mode,
the shift is an integral part of the filter, and determines
the cut-off frequency of the filter. Table 31-4 shows the
-3 dB cut-off frequency in ωT (radians) and the highest
signal attenuation obtained by this filter at nyquist
frequency (ωT = π).
TABLE 31-4: LOW-PASS FILTER -3 dB CUT-OFF FREQUENCY
ADCRS
ωT (radians) @ -3 dB Frequency
1
0.72
2
0.284
3
0.134
4
0.065
5
0.032
6
0.016
7
0.0078
dB @ F_nyquist=1/(2T)
-9.5
-16.9
-23.5
-29.8
-36.0
-42.0
-48.1
31.5.2 BASIC MODE
Basic mode (ADMD = 000) disables all additional
computation features. In this mode, no accumulation
occurs but threshold error comparison is performed.
Double sampling, Continuous mode, and all CVD
features are still available, but no features involving the
digital filter/average features are used.
31.5.3 ACCUMULATE MODE
In Accumulate mode (ADMD = 001), after every
conversion, the ADC result is added to the ADACC
register. The ADACC register is right-shifted by the
value of the ADCRS bits in the ADCON2 register. This
right-shifted value is copied in to the ADFLT register.
The Formatting mode does not affect the
right-justification of the ADACC value. Upon each
sample, ADCNT is also incremented, incrementing the
number of samples accumulated. After each sample
and accumulation, the ADACC value has a threshold
comparison performed on it (see Section
31.5.7 “Threshold Comparison”) and the ADTIF
interrupt may trigger.
31.5.4 AVERAGE MODE
In Average Mode (ADMD = 010), the ADACC registers
accumulate with each ADC sample, much as in
Accumulate mode, and the ADCNT register increments
with each sample. The ADFLT register is also updated
with the right-shifted value of the ADACC register. The
value of the ADCRS bits governs the number of right
shifts. However, in Average mode, the threshold
comparison is performed upon ADCNT being greater
than or equal to a user-defined ADRPT value. In this
mode when ADRPT = 2^ADCNT, then the final
accumulated value will be divided by number of
samples, allowing for a threshold comparison operation
on the average of all gathered samples.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 441