PIC18LF24K Datasheet, PDF (221/594 Pages) –

PIC18(L)F26/45/46K40
18.1 Timer0 Operation
Timer0 can operate as either an 8-bit timer/counter or
a 16-bit timer/counter. The mode is selected with the
T016BIT bit of the T0CON register.
18.1.1 16-BIT MODE
The register pair TMR0H:TMR0L, increments on the
rising edge of the clock source. A 15-bit prescaler on
the clock input gives several prescale options (see
prescaler control bits, T0CKPS<3:0> in the T0CON1
register).
18.1.1.1 Timer0 Reads and Writes in 16-Bit
Mode
In 16-bit mode, to avoid rollover between reading high
and low registers, the TMR0H register is a buffered
copy of the actual high byte of Timer0, which is neither
directly readable nor writable (see Figure 18-1).
TMR0H is updated with the contents of the high byte of
Timer0 during a read of TMR0L. This provides the
ability to read all 16 bits of Timer0 without having to
verify that the read of the high and low byte was valid,
due to a rollover between successive reads of the high
and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
18.1.2 8-BIT MODE
In normal operation, TMR0 increments on the rising
edge of the clock source. A 15-bit prescaler on the
clock input gives several prescale options (see
prescaler control bits, T0CKPS<3:0> in the T0CON1
register).
In 8-bit mode, the value of TMR0L is compared to that
of the Period buffer, a copy of TMR0H, on each clock
cycle. When the two values match, the following events
happen:
• TMR0_out goes high for one prescaled clock
period
• TMR0L is reset
• The contents of TMR0H are copied to the period
buffer
In 8-bit mode, the TMR0L and TMR0H registers are
both directly readable and writable. The TMR0L
register is cleared on any device Reset, while the
TMR0H register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• A write to the TMR0L register
• A write to either the T0CON0 or T0CON1
registers
• Any device Reset – Power-on Reset (POR),
MCLR Reset, Watchdog Timer Reset (WDTR) or
• Brown-out Reset (BOR)
18.1.3 COUNTER MODE
In Counter mode, the prescaler is normally disabled by
setting the T0CKPS bits of the T0CON1 register to
‘0000’. Each rising edge of the clock input (or the
output of the prescaler if the prescaler is used)
increments the counter by ‘1’.
18.1.4 TIMER MODE
In Timer mode, the Timer0 module will increment every
instruction cycle as long as there is a valid clock signal
and the T0CKPS bits of the T0CON1 register
(Register 18-2) are set to ‘0000’. When a prescaler is
added, the timer will increment at the rate based on the
prescaler value.
18.1.5 ASYNCHRONOUS MODE
When the T0ASYNC bit of the T0CON1 register is set
(T0ASYNC = ‘1’), the counter increments with each
rising edge of the input source (or output of the
prescaler, if used). Asynchronous mode allows the
counter to continue operation during Sleep mode
provided that the clock also continues to operate during
Sleep.
18.1.6 SYNCHRONOUS MODE
When the T0ASYNC bit of the T0CON1 register is clear
(T0ASYNC = 0), the counter clock is synchronized to
the system clock (FOSC/4). When operating in
Synchronous mode, the counter clock frequency
cannot exceed FOSC/4.
18.2 Clock Source Selection
The T0CS<2:0> bits of the T0CON1 register are used
to select the clock source for Timer0. Register 18-2
displays the clock source selections.
18.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected, Timer0
operates as a timer and will increment on multiples of
the clock source, as determined by the Timer0
prescaler.
18.2.2 EXTERNAL CLOCK SOURCE
When an external clock source is selected, Timer0 can
operate as either a timer or a counter. Timer0 will
increment on multiples of the rising edge of the external
clock source, as determined by the Timer0 prescaler.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 221