PIC18LF24K Datasheet, PDF (332/594 Pages) –

PIC18(L)F26/45/46K40
26.4 Register Definitions: MSSP Control
REGISTER 26-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE⁽¹⁾
D/A
P
S
R/W
UA
bit 7
R-0
BF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit⁽¹⁾
1 = Transmit occurs on the transition from active to Idle clock state
0 = Transmit occurs on the transition from Idle to active clock state
bit 5
D/A: Data/Address bit
Used in I²C mode only.
bit 4
P: Stop bit
Used in I²C mode only. This bit is cleared when the MSSPx module is disabled; SSPEN is cleared.
bit 3
S: Start bit
Used in I²C mode only.
bit 2
R/W: Read/Write Information bit
Used in I²C mode only.
bit 1
UA: Update Address bit
Used in I²C mode only.
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive is complete, SSPxBUF is full
0 = Receive is not complete, SSPxBUF is empty
Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 332