PIC18LF24K Datasheet, PDF (444/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 31-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
ADPPOL
ADIPEN
ADGPOL
—
—
—
bit 7
U-0
R/W-0/0
—
ADDSEN
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4-1
bit 0
ADDPOL: Precharge Polarity bit
If ADPRE>0x00:
ADPPOL
1
0
Action During 1st Precharge Stage
External (selected analog I/O pin)
Shorted to AVDD
Shorted to VSS
Internal (AD sampling capacitor)
C_HOLD shorted to VSS
C_HOLD shorted to AVDD
Otherwise:
The bit is ignored
ADIPEN: A/D Inverted Precharge Enable bit
If ADDSEN = 1
1 = The precharge and guard signals in the second conversion cycle are the opposite polarity of the
first cycle
0 = Both Conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL
Otherwise:
The bit is ignored
ADGPOL: Guard Ring Polarity Selection bit
1 = ADC guard Ring outputs start as digital high during Precharge stage
0 = ADC guard Ring outputs start as digital low during Precharge stage
Unimplemented: Read as ‘0’
ADDSEN: Double-sample enable bit
1 = Two conversions are performed on each trigger. Data from the first conversion appears in
ADPREV
0 = One conversion is performed for each trigger
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 444