PIC18LF24K Datasheet, PDF (345/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 26-10:
MSSP BLOCK DIAGRAM (I²C SLAVE MODE)
Read
Internal
Data Bus
Write
SCL
SDA
SSPxCLKPPS⁽²⁾
PPS
PPS
Clock
Stretching
RxyPPS⁽²⁾
SSPxDATPPS⁽¹⁾
PPS
PPS
RxyPPS⁽¹⁾
SSPxBUF Reg
Shift
Clock
SSPSR Reg
MSb
LSb
SSPxMSK Reg
Match Detect
Addr Match
SSPxADD Reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT Reg)
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
The I²C bus specifies two signal connections:
• Serial Clock (SCL)
• Serial Data (SDA)
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
Figure 26-11 shows a typical connection between two
processors configured as master and slave devices.
The I²C bus can operate with one or more master
devices and one or more slave devices.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a
single Read/Write bit, which determines whether the
master intends to transmit to or receive data from the
slave device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
FIGURE 26-11:
I²C MASTER/
SLAVE CONNECTION
VDD
SCL
VDD
Master
SDA
SCL
Slave
SDA
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDA line low to indicate to the transmit-
ter that the slave device has received the transmitted
data and is ready to receive more.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 345