PIC18LF24K Datasheet, PDF (138/594 Pages) –

PIC18(L)F26/45/46K40
11.1.6.2 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit. Since
program memory is stored as a full page, the stored
program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 11-10:
PROGRAM FLASH
MEMORY VERIFY
FLOWCHART
Rev. 10-000051B
12/4/2015
Start
Verify Operation
This routine assumes that the last
row of data written was from an
image saved on RAM. This image
will be used to verify the data
currently stored in PFM
Read Operation⁽¹⁾
NVMDAT =
No
RAM image ?
Yes
Fail
Verify Operation
No
Last word ?
Yes
End
Verify Operation
11.1.6.3
Unexpected Termination of Write
Operation
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
11.1.6.4 Protection Against Spurious Writes
A write sequence is valid only when both the following
conditions are met, this prevents spurious writes which
might lead to data corruption.
1. The WR bit is gated through the WREN bit. It is
suggested to have the WREN bit cleared at all
times except during memory writes. This
prevents memory writes if the WR bit gets set
accidentally.
2. The NVM unlock sequence must be performed
each time before a write operation.
11.2 User ID, Device ID and
Configuration Word Access
When NVMREG<1:0> = 0x01 or 0x11 in the
NVMCON1 register, the User ID’s, Device ID/
Revision ID and Configuration Words can be
accessed. Different access may exist for reads and
writes (see Table 11-3).
11.2.1 Reading Access
The user can read from these blocks by setting the
NVMREG bits to 0x01 or 0x11. The user needs to load
the address into the TBLPTR registers. Executing a
TBLRD after that moves the byte pointed to the TAB-
LAT register. The CPU operation is suspended during
the read and resumes after. When read access is initi-
ated on an address outside the parameters listed in
Table 11-3, the TABLAT register is cleared, reading
back ‘0’s.
11.2.2 Writing Access
The WREN bit in NVMCON1 must be set to enable
writes. This prevents accidental writes to the CONFIG
words due to errant (unexpected) code execution. The
WREN bit should be kept clear at all times, except
when updating the CONFIG words. The WREN bit is
not cleared by hardware. The WR bit will be inhibited
from being set unless the WREN bit is set.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 138