PIC18LF24K Datasheet, PDF (334/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 26-3: SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE)
R/HS/HC-0
ACKTIM
R/W-0
PCIE⁽¹⁾
R/W-0
SCIE⁽¹⁾
R/W-0
BOEN⁽²⁾
R/W-0
SDAHT
R/W-0
SBCDE
bit 7
R/W-0
AHEN
R/W-0
DHEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
x = Bit is unknown
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
HS/HC = Bit is set/cleared by hardware
bit 7
ACKTIM: Acknowledge Time Status bit
Unused in SPI.
bit 6
PCIE: Stop Condition Interrupt Enable bit⁽¹⁾
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 5
SCIE: Start Condition Interrupt Enable bit⁽¹⁾
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 4
BOEN: Buffer Overwrite Enable bit⁽²⁾
1 = SSPxBUF updates every time a new data byte is shifted in, ignoring the BF bit
0 = If a new byte is received with BF bit already set, SSPOV is set, and the buffer is not updated
bit 3
SDAHT: SDA Hold Time Selection bit
Unused in SPI.
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit
Unused in SPI.
bit 1
AHEN: Address Hold Enable bit
Unused in SPI.
bit 0
DHEN: Data Hold Enable bit
Unused in SPI.
Note 1:
2:
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 334