PIC18LF24K Datasheet, PDF (29/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 3-9:
U-1
—
bit 7
Configuration Word 5L (30 0008h): Code Protection
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
R/W-1
CPD
R/W-1
CP
bit 0
Legend:
R = Readable bit
-n = Value for blank device
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘1’
CPD: Data NVM Memory Code Protection bit
1 = Data NVM code protection disabled
0 = Data NVM code protection enabled
CP: User NVM Program Memory Code Protection bit
1 = User NVM code protection disabled
0 = User NVM code protection enabled
REGISTER 3-10: Configuration Word 6L (30 000Ah): Memory Read Protection
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
EBTR7
EBTR6
EBTR5
EBTR4
EBTR3
EBTR2
EBTR1
bit 7
R/W-1
EBTR0
bit 0
Legend:
R = Readable bit
-n = Value for blank device
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
EBTR<7:0>: Table Read Protection bits⁽¹⁾
1 = Corresponding Memory Block NOT protected from table reads executed in other blocks
0 = Corresponding Memory Block protected from table reads executed in other blocks
Note 1: Refer to Table 10-2 for details on implementation of the individual EBTR bits.
REGISTER 3-11:
U-1
—
bit 7
Configuration Word 6H (30 000Bh): Memory Read Protection
U-1
U-1
U-1
U-1
U-1
R/W-1
—
—
—
—
—
EBTRB
U-1
—
bit 0
Legend:
R = Readable bit
-n = Value for blank device
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘1’
EBTRB: Table Read Protection bit
1 = Memory Boot Block NOT protected from table reads executed in other blocks
0 = Memory Boot Block protected from table reads executed in other blocks
Unimplemented: Read as ‘1’
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 29