PIC18LF24K Datasheet, PDF (181/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 14-13: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0/0
R/W-0/0
R/W-0/0
R-/W0/0
R/W-0/0
R/W-0/0
RC2IE
TX2IE
RC1IE
TX1IE
BCL2IE
SSP2IE
bit 7
R/W-0/0
BCL1IE
R/W-0/0
SSP1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5
RC1IE: EUSART1 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX1IE: EUSART1 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
SSP2IE: Synchronous Serial Port 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
SSP1IE: Synchronous Serial Port 1 Interrupt Enable bit
1 = Enabled
0 = Disabled
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 181