PIC18LF24K Datasheet, PDF (185/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 14-17: PIE7: PERIPHERAL INTERRUPT ENABLE REGISTER 7
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
SCANIE
CRCIE
NVMIE
—
—
—
—
bit 7
R/W-0/0
CWG1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4-1
bit 0
SCANIE: SCAN Interrupt Enable bit
1 = Enabled
0 = Disabled
CRCIE: CRC Interrupt Enable bit
1 = Enabled
0 = Disabled
NVMIE: NVM Interrupt Enable bit
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
CWG1IE: CWG Interrupt Enable bit
1 = Enabled
0 = Disabled
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 185