PIC18LF24K Datasheet, PDF (197/594 Pages) –

PIC18(L)F26/45/46K40
15.1 I/O Priorities
Each pin defaults to the PORT data latch after Reset.
Other functions are selected with the peripheral pin
select logic. See Section 17.0 “Peripheral Pin Select
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs, are not shown in the peripheral pin select lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELx register. Digital output
functions may continue to control the pin when it is in
Analog mode.
Analog outputs, when enabled, take priority over digital
outputs and force the digital output driver into a
high-impedance state.
The pin function priorities are as follows:
1. Configuration bits
2. Analog outputs (disable the input buffers)
3. Analog inputs
4. Port inputs and outputs from PPS
15.2 PORTx Registers
In this section the generic names such as PORTx,
LATx, TRISx, etc. can be associated with PORTA,
PORTB, PORTC and PORTD. For availability of
PORTD refer to Table 15-1. The functionality of
PORTE is different compared to other ports and is
explained in a separate section.
15.2.1 DATA REGISTER
PORTx is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISx
(Register 15-2). Setting a TRISx bit (‘1’) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISx bit (‘0’) will make the
corresponding PORTx pin an output (i.e., it enables
output driver and puts the contents of the output latch
on the selected pin). Example 15-1 shows how to
initialize PORTx.
Reading the PORTx register (Register 15-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATx).
The PORT data latch LATx (Register 15-3) holds the
output port data and contains the latest value of a LATx
or PORTx write.
EXAMPLE 15-1: INITIALIZING PORTA
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
BANKSEL PORTA
;
CLRF PORTA
;Init PORTA
BANKSEL LATA
;Data Latch
CLRF LATA
;
BANKSEL ANSELA
;
CLRF ANSELA
;digital I/O
BANKSEL TRISA
;
MOVLW B'11111000' ;Set RA<7:3> as inputs
MOVWF TRISA
;and set RA<2:0> as
;outputs
15.2.2 DIRECTION CONTROL
The TRISx register (Register 15-2) controls the PORTx
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISx register are maintained set when using them as
analog inputs. I/O pins configured as analog inputs
always read ‘0’.
15.2.3 ANALOG CONTROL
The ANSELx register (Register 15-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELx bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELx bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELx bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
15.2.4 OPEN-DRAIN CONTROL
The ODCONx register (Register 15-6) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONx bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONx bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
Note:
It is not necessary to set open-drain
control when using the pin for I²C; the I²C
module controls the pin and makes the pin
open-drain.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 197