PIC18LF24K Datasheet, PDF (81/594 Pages) –

PIC18(L)F26/45/46K40
8.14 Power Control (PCON0) Register
The Power Control (PCON0) register contains flag bits
to differentiate between a:
• Brown-out Reset (BOR)
• Power-on Reset (POR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Watchdog Window Violation (WDTWV)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON0 register bits are shown in Register 8-2.
Hardware will change the corresponding register bit
during the Reset process; if the Reset was not caused
by the condition, the bit remains unchanged
(Table 8-3).
Software should reset the bit to the inactive state after
restart (hardware will not reset the bit).
Software may also set any PCON0 bit to the active
state, so that user code may be tested, but no Reset
action will be generated.
TABLE 8-4: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON SBOREN —
—
—
—
—
—
BORRDY
74
PCON0
STKOVF STKUNF WDTWV RWDT RMCLR
RI
POR
BOR
75
STATUS
—
TO
PD
N
OV
Z
DC
C
117
WDTCON0
—
—
WDTPS<4:0>
SEN
84
WDTCON1
—
WDTCS<2:0>
—
WINDOW<2:0>
85
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 81