PIC18LF24K Datasheet, PDF (329/594 Pages) –

PIC18(L)F26/45/46K40
26.0 MASTER SYNCHRONOUS
SERIAL PORT MODULE
Note:
The PIC18(L)F26/45/46K40 devices have
two MSSP. Therefore, all information in
this section refers to both MSSP1 and
MSSP2.
26.1 MSSP Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The
PIC18(L)F26/45/46K40 devices have two MSSP
modules that can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I²C)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
The I²C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
26.2 SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication. A slave device is
controlled through a Chip Select known as Slave
Select.
The SPI bus specifies four signal connections:
• Serial Clock (SCK)
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Slave Select (SS)
Figure 26-1 shows the block diagram of the MSSP
module when operating in SPI mode.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 329