PIC18LF24K Datasheet, PDF (416/594 Pages) –

PIC18(L)F26/45/46K40
27.6 EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the neces-
sary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
27.6.1
SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCxSTA and TXxSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 27.5.2.4 “Synchronous Slave
Reception Setup:”).
• If interrupts are desired, set the RCxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
• The RCxIF interrupt flag must be cleared by read-
ing RCxREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RXx/DTx and TXx/CKx
pins, respectively. When the data word has been com-
pletely clocked in by the external device, the RCxIF
interrupt flag bit of the PIR3 register will be set.
Thereby, waking the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.
27.6.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• The RCxSTA and TXxSTA Control registers must
be configured for synchronous slave transmission
(see Section 27.5.2.2 “Synchronous Slave
Transmission Setup”).
• The TXxIF interrupt flag must be cleared by writ-
ing the output data to the TXxREG, thereby filling
the TSR and transmit buffer.
• If interrupts are desired, set the TXxIE bit of the
PIE3 register and the PEIE bit of the INTCON
register.
• Interrupt enable bits TXxIE of the PIE3 register
and PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TXx/CKx pin and transmit data on the
RXx/DTx pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXxREG will transfer to the TSR
and the TXxIF flag will be set. Thereby, waking the pro-
cessor from Sleep. At this point, the TXxREG is avail-
able to accept another character for transmission,
which will clear the TXxIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 416