PIC18LF24K Datasheet, PDF (133/594 Pages) –

FIGURE 11-7:
PFM ROW ERASE
FLOWCHART
Start Erase Operation
Select Memory:
PFM (NVMREGS<1:0> = 10)
Load Table Pointer register with
address of the block being erased
Select Erase Operation
(FREE = 1)
Enable Write/Erase Operation
(WREN = 1)
Disable Interrupts
(GIE = 0)
Unlock Sequence
(Figure 11-6)
CPU stalls while Erase operation
completes (2 ms typical)
Enable Interrupts
(GIE = 1)
Disable Write/Erase Operation
(WREN = 0)
End Erase Operation
PIC18(L)F26/45/46K40
11.1.6
WRITING TO PROGRAM FLASH
MEMORY
The programming write block size is described in
Table 11-3. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes in
a write block. Refer to Table 11-3 for write latch size.
Since the table latch (TABLAT) is only a single byte, the
TBLWT instruction needs to be executed multiple times
for each programming operation. The write protection
state is ignored for this operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. NVMIF is not affected
while writing to the holding registers.
After all the holding registers have been written, the
programming operation of that block of memory is
started by configuring the NVMCON1 register for a
program memory write and performing the long write
sequence.
If the PFM address in the TBLPTR is write-protected or
if TBLPTR points to an invalid location, the WR bit is
cleared without any effect and the WREER is signaled.
The long write is necessary for programming the
internal Flash. CPU operation is suspended during a
long write cycle and resumes when the operation is
complete. The long write operation completes in one
instruction cycle. When complete, WR is cleared in
hardware and NVMIF is set and an interrupt will occur if
NVMIE is also set. The latched data is reset to all ‘1s’.
WREN is not changed.
The internal programming timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range of
the device.
Note:
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may
be modified, provided that the change does
not attempt to change any bit from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all holding registers
before executing a long write operation.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 133