PIC18LF24K Datasheet, PDF (57/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 5-2:
U-0
—
bit 7
CLKRCLK: CLOCK REFERENCE CLOCK SELECTION MUX
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
—
—
CLK<2:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
CLK<2:0>: CLKR Clock Selection bits
111 = Unimplemented
110 = Unimplemented
101 = Unimplemented
100 = SOSC
011 = MFINTOSC (500 kHz)
010 = LFINTOSC (31 kHz)
001 = HFINTOSC
000 = FOSC
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CLKRCON
EN
—
—
DC<1:0>
DIV<2:0>
56
CLKRCLK
—
—
—
—
—
CLK<2:0>
57
PMD0
SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD
CLKRMD
IOCMD
67
RxyPPS
—
—
—
RxyPPS<4:0>
217
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 57