PIC18LF24K Datasheet, PDF (384/594 Pages) –

PIC18(L)F26/45/46K40
26.11 Baud Rate Generator
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I²C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 26-5).
When a write occurs to SSPxBUF, the Baud Rate
Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 26-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
being operated in.
Table 26-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
EQUATION 26-1:
FCLOCK = _---S---S----P----A----FD---^O-D---^S--^C-+------1---_---_--4----_
FIGURE 26-40: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPxADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
SSPCLK
BRG Down Counter
FOSC/2
Note:
Values of 0x00, 0x01 and 0x02 are not valid
for SSPxADD when used as a Baud Rate
Generator for I²C. This is an implementation
limitation.
TABLE 26-3: MSSP CLOCK RATE W/BRG
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
Note:
32 MHz
8 MHz
13h
400 kHz
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Refer to the I/O port electrical specifications in Table 37-8: Internal Oscillator Parameters, to ensure the sys-
tem is designed to support IOL requirements.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 384