PIC18LF24K Datasheet, PDF (246/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 20-4: TxHLT: TIMERx HARDWARE LIMIT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSYNC
CPOL
CSYNC
MODE<4:0>
bit 7
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4-0
PSYNC: Timerx Prescaler Synchronization Enable bit^{(1, 2)}
1 = TMRx Prescaler Output is synchronized to Fosc/4
0 = TMRx Prescaler Output is not synchronized to Fosc/4
CPOL: Timerx Clock Polarity Selection bit⁽³⁾
1 = Falling edge of input clock clocks timer/prescaler
0 = Rising edge of input clock clocks timer/prescaler
CSYNC: Timerx Clock Synchronization Enable bit^{(4, 5)}
1 = ON register bit is synchronized to TMR2_clk input
0 = ON register bit is not synchronized to TMR2_clk input
MODE<4:0>: Timerx Control Mode Selection bits^{(6, 7)}
See Table 20-2 for all operating modes.
Note 1: Setting this bit ensures that reading TMRx will return a valid data value.
2: When this bit is ‘1’, Timer2 cannot operate in Sleep mode.
3: CKPOL should not be changed while ON = 1.
4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set.
6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without
affecting the value of TMRx).
7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 246