PIC18LF24K Datasheet, PDF (356/594 Pages) –

PIC18(L)F26/45/46K40
26.9.2.1 7-bit Addressing Reception
This section describes a standard sequence of events
for the MSSP module configured as an I²C slave in
7-bit Addressing mode. Figure 26-14 and Figure 26-15
is used as a visual reference for this description.
This is a step by step process of what typically must
be done to accomplish I²C communication.
1. Start bit detected.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
3. Matching address with R/W bit clear is received.
4. The slave pulls SDA low sending an ACK to the
master, and sets SSPxIF bit.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. If SEN = 1; Slave software sets CKP bit to
release the SCL line.
8. The master clocks out a data byte.
9. Slave drives SDA low sending an ACK to the
master, and sets SSPxIF bit.
10. Software clears SSPxIF.
11. Software reads the received byte from
SSPxBUF clearing BF.
12. Steps 8-12 are repeated for all received bytes
from the master.
13. Master sends Stop condition, setting P bit of
SSPxSTAT, and the bus goes idle.
26.9.2.2 7-bit Reception with AHEN and
DHEN
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the eighth
falling edge of SCL. These additional interrupts allow
the slave software to decide whether it wants to ACK
the receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I²C communi-
cation. Figure 26-16 displays a module using both
address and data holding. Figure 26-17 includes the
operation with the SEN bit of the SSPxCON2 register
set.
1. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSPxIF is set and CKP cleared after the
eighth falling edge of SCL.
3. Slave clears the SSPxIF.
4. Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if the SSPxIF
was after or before the ACK.
5. Slave reads the address value from SSPxBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
8. SSPxIF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPxIF.
Note: SSPxIF is still set after the ninth falling edge
of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to master is SSPxIF not set
11. SSPxIF set and CKP cleared after eighth falling
edge of SCL for a received data byte.
12. Slave looks at ACKTIM bit of SSPxCON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSPxBUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 356