PIC18LF24K Datasheet, PDF (139/594 Pages) –

PIC18(L)F26/45/46K40
The user needs to load the TBLPTR and TABLAT reg-
ister with the address and data byte respectively before
executing the write command. An unlock sequence
needs to be followed for writing to the USER IDs/
DEVICE IDs/CONFIG words (Section 11.1.4, NVM
Unlock Sequence). If WRTC = 0 or if TBLPTR points
an invalid address location (see Table 11-3), WR bit is
cleared without any effect and WRERR is set.
A single CONFIG word byte is written at once and the
operation includes an implicit erase cycle for that byte
(it is not necessary to set FREE). CPU execution is
stalled and at the completion of the write cycle, the WR
bit is cleared in hardware and the NVM Interrupt Flag
bit (NVMIF) is set. The new CONFIG value takes effect
when the CPU resumes operation.
TABLE 11-4: USER ID, DEV/REV ID AND CONFIGURATION WORD ACCESS (NVMREG<1:0> = X1)
Address
Function
Read Access
Write Access
20 0000h-20 000Fh
User IDs
Yes
Yes
3F FFFCh-3F FFFFh
Revision ID/Device ID
Yes
No
30 0000h-30 000Bh
Configuration Words 1-6
Yes
Yes
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 139