PIC18LF24K Datasheet, PDF (216/594 Pages) –

PIC18(L)F26/45/46K40
TABLE 17-1: PPS INPUT REGISTER DETAILS
Peripheral
PPS Input
Register
Default Pin
Selection
at POR
Interrupt 0
INT0PPS
RB0
Interrupt 1
INT1PPS
RB1
Interrupt 2
INT2PPS
RB2
Timer0 Clock
T0CKIPPS
RA4
Timer1 Clock
T1CKIPPS
RC0
Timer1 Gate
T1GPPS
RB5
Timer3 Clock
T3CKIPPS
RC0
Timer3 Gate
T3GPPS
RC0
Timer5 Clock
T5CKIPPS
RC2
Timer5 Gate
T5GPPS
RB4
Timer2 Clock
T2INPPS
RC3
Timer4 Clock
T4INPPS
RC5
Timer6 Clock
T6INPPS
RB7
CCP1
CCP1PPS
RC2
CCP2
CCP2PPS
RC1
CWG
CWG1PPS
RB0
DSM Carrier Low
MDCARLPPS
RA3
DSM Carrier High
MDCARHPPS
RA4
DSM Source
MDSRCPPS
RA5
ADC Conversion Trigger ADACTPPS
RB4
MSSP1 Clock
SSP1CLKPPS
RC3
MSSP1 Data
SSP1DATPPS
RC4
MSSP1 Slave Select
SSP1SSPPS
RA5
MSSP2 Clock
SSP2CLKPPS
RB1
MSSP2 Data
SSP2DATPPS
RB2
MSSP2 Slave Select
SSP2SSPPS
RB0
EUSART1 Receive
RX1PPS
RC7
EUSART1 Transmit
TX1PPS
RC6
EUSART2 Receive
RX2PPS
RB7
EUSART2 Transmit
TX2PPS
RB6
Register Reset Input Available from Selected PORTx
Value
at POR
PIC18(L)F26K40 PIC18(L)F45/46K40
5’b0 1000
A B — A B ——
5’b0 1001
A B — A B ——
5’b0 1010
A B — A B ——
5’b0 0100
A B — A B ——
5’b1 0000
A — C A—C—
5’b0 1101
5’b1 0000
5’b1 0000
5’b1 0010
5’b0 1100
5’b1 0011
5’b1 0101
5’b0 1111
5’b1 0010
5’b1 0001
5’b0 1000
5’b0 0011
5’b0 0100
5’b0 0101
5’b0 1100
5’b1 0011
5’b1 0100
5’b0 0101
5’b0 1001
5’b0 1010
5’b0 1000
5’b1 0111
5’b1 0110
5’b0 1111
5’b0 1110
— B C—B C—
— ^{B C—B C—}
A _— C A—C—
A _— C A—C—
— ^{B C—B—D}
A _— C A—C—
— ^{B C—B C—}
— ^{B C—B—D}
— B C—B C—
— B C—B C—
— B C—B—D
A _— C A —— D
A _— C A —— D
A _— C A —— D
— B C—B—D
— B C—B C—
— _{B C—B C—}
A — C A ^—— D
— B C—B—D
— B C—B—D
— B C—B—D
— B C—B C—
— B C—B C—
— B C—B—D
— B C—B—D
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 216