PIC18LF24K Datasheet, PDF (50/594 Pages) –

PIC18(L)F26/45/46K40
4.5 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, ECL/M/H and
Secondary Oscillator).
FIGURE 4-9:
External
Clock
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
SQ
LFINTOSC
Oscillator
31 kHz
(~32 s)
÷ 64
488 Hz
(~2 ms)
Sample Clock
R
Q
Clock
Failure
Detected
4.5.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 4-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
4.5.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM overwrites the
COSC bits to select HFINTOSC (3'b110). The
frequency of HFINTOSC would be determined by the
previous state of the HFFRQ bits and the NDIV/CDIV
bits. The bit flag OSCFIF of the PIR1 register is set.
Setting this flag will generate an interrupt if the OSCFIE
bit of the PIE1 register is also set. The device firmware
can then take steps to mitigate the problems that may
arise from a failed clock. The system clock will continue
to be sourced from the internal clock source until the
device firmware successfully restarts the external
oscillator and switches back to external operation, by
writing to the NOSC and NDIV bits of the OSCCON1
register.
4.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the NOSC
and NDIV bits of the OSCCON1 register. When
switching to the external oscillator or PLL, the OST is
restarted. While the OST is running, the device
continues to operate from the INTOSC selected in
OSCCON1. When the OST times out, the Fail-Safe
condition is cleared after successfully switching to the
external clock source. The OSCFIF bit should be
cleared prior to switching to the external clock source.
If the Fail-Safe condition still exists, the OSCFIF flag
will again become set by hardware.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 50