PIC18LF24K Datasheet, PDF (262/594 Pages) –

PIC18(L)F26/45/46K40
TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCPTMRS
P4TSEL<1:0>
P3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
INTCON
GIE/GIEH PEIE/GIEL IPEN
—
—
INT2EDG INT1EDG INT0EDG
PIE4
PIR4
—
—
TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE
—
—
TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF
IPR4
—
—
TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP
PMD1
PR2
—
TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD
Timer2 Module Period Register
TMR2
Holding Register for the 8-bit TMR2 Register
T2CON
ON
CKPS<2:0>
OUTPS<3:0>
T2CLKCON
T2RST
T2HLT
PR4
—
—
PSYNC
—
—
CPOL
—
—
—
CS<2:0>
—
—
RSEL<3:0>
CSYNC
MODE<4:0>
Timer4 Module Period Register
TMR4
Holding Register for the 8-bit TMR4 Register
T4CON
ON
CKPS<2:0>
OUTPS<3:0>
T4CLKCON
—
—
—
—
—
CS<2:0>
T4RST
—
—
—
—
RSEL<3:0>
T4HLT
PR6
PSYNC
CPOL
CSYNC
MODE<4:0>
Timer6 Module Period Register
TMR6
Holding Register for the 8-bit TMR6 Register
T6CON
ON
CKPS<2:0>
OUTPS<3:0>
T6CLKCON
—
—
—
—
T6RST
—
—
—
—
T6HLT
PSYNC
CPOL
CSYNC
T2INPPS
—
—
—
—
CS<2:0>
RSEL<3:0>
MODE<4:0>
T2INPPS<4:0>
T4INPPS
—
—
—
T4INPPS<4:0>
T6INPPS
Legend:
*
—
—
—
T6INPPS<4:0>
— = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
Page provides register information.
Register
on Page
266
169
182
174
190
68
250*
250*
245
248
249
246
250*
250*
245
248
249
246
250*
250*
245
248
249
246
215
215
215
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 262