PIC18LF24K Datasheet, PDF (37/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 4-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2
U-0
R-q/q
R-q/q
R-q/q
R-q/q
R-q/q
R-q/q
—
COSC<2:0>
CDIV<3:0>
bit 7
R-q/q
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Reset value is determined by hardware
bit 7
bit 6-4
bit 3-0
Unimplemented: Read as ‘0’
COSC<2:0>: Current Oscillator Source Select bits (read-only)^(1,2)
Indicates the current source oscillator and PLL combination per Table 4-2.
CDIV<3:0>: Current Divider Select bits (read-only)^(1,2)
Indicates the current postscaler division ratio per Table 4-2.
Note 1: The POR value is the value present when user code execution begins.
2: The Reset value (q/q) is the same as the NOSC/NDIV bits.
TABLE 4-2: NOSC/COSC AND NDIV/CDIV BIT SETTINGS
NOSC<2:0>
COSC<2:0>
111
110
101
100
011
010
001
000
Clock Source
EXTOSC⁽¹⁾
HFINTOSC⁽²⁾
LFINTOSC
SOSC
Reserved
EXTOSC + 4x PLL⁽³⁾
Reserved
Reserved
NDIV<3:0>
CDIV<3:0>
1111-1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Clock Divider
Reserved
512
256
128
64
32
16
8
4
2
1
Note 1:
2:
3:
EXTOSC configured by the FEXTOSC bits of Configuration Word 1 (Register 3-1).
HFINTOSC frequency is set with the HFFRQ bits of the OSCFRQ register (Register 4-5).
EXTOSC must meet the PLL specifications (Table 37-9).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 37