PIC18LF24K Datasheet, PDF (503/594 Pages) –

PIC18(L)F26/45/46K40
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Inclusive OR literal with W
IORLW k
0  k  255
(W) .OR. k  W
N, Z
0000 1001 kkkk kkkk
The contents of W are ORed with the 8-
bit literal ‘k’. The result is placed in W.
1
1
Q2
Read
literal ‘k’
Q3
Process
Data
Q4
Write to W
Example:
IORLW
35h
Before Instruction
W
= 9Ah
After Instruction
W
= BFh
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Inclusive OR W with f
IORWF f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
(W) .OR. (f)  dest
N, Z
0001 00da ffff ffff
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See Sec-
tion 35.2.3 “Byte-Oriented and Bit-
Oriented Instructions in Indexed Lit-
eral Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W
= 91h
After Instruction
RESULT = 13h
W
= 93h
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 503