PIC18LF24K Datasheet, PDF (337/594 Pages) –

PIC18(L)F26/45/46K40
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the
next byte of data to transfer is written to the SSPxBUF.
The Buffer Full bit, BF of the SSPxSTAT register,
indicates when SSPxBUF has been loaded with the
received data (transmission is complete). When the
SSPxBUF is read, the BF bit is cleared. This data may
be irrelevant if the SPI is only a transmitter. Generally,
the MSSP interrupt is used to determine when the
transmission/reception has completed. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPxBUF register.
Additionally, the SSPxSTAT register indicates the
various Status conditions.
FIGURE 26-3:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010 _SDO
Serial Input Buffer
(BUF)
SPI Slave SSPM<3:0> = 010x
SDI
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPSR)
MSb
LSb
SDI
SCK
Serial Clock
SDO
SCK
Shift Register
(SSPSR)
MSb
LSb
Processor 1
General I/O
Slave Select
(optional)
SS
Processor 2
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 337