PIC18LF24K Datasheet, PDF (143/594 Pages) –

PIC18(L)F26/45/46K40
11.3.6
OPERATION DURING CODE-
PROTECT
Data EEPROM Memory has its own code-protect bits in
Configuration Words. External read and write operations
are disabled if code protection is enabled.
If the Data EEPROM is write-protected or if NVMADR
points an invalid address location, the WR bit is cleared
without any effect. WRERR is signaled in this scenario.
11.3.7
PROTECTION AGAINST SPURIOUS
WRITE
There are conditions when the user may not want to
write to the Data EEPROM Memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT).
The unlock sequence and the WREN bit together help
prevent an accidental write during brown-out, power
glitch or software malfunction.
11.3.8
ERASING THE DATA EEPROM
MEMORY
Data EEPROM Memory can be erased by writing 0xFF
to all locations in the Data EEPROM Memory that
needs to be erased.
EXAMPLE 11-7:
Loop
CLRF
CLRF
BCF
BCF
SETF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
DATA EEPROM REFRESH ROUTINE
NVMADRL
NVMADRH
NVMCON1, NVMREG0
NVMCON1, NVMREG1
NVMDAT
INTCON, GIE
NVMCON1, WREN
0x55
NVMCON2
0xAA
NVMCON2
NVMCON1, WR
NVMCON1, WR
$-2
NVMADRL, F
Loop
; Clear address low byte register
; Clear address high byte register (if applicable)
; Set access for EEPROM
; Set access for EEPROM
; Load 0xFF to data register
; Disable interrupts
; Enable writes
; Loop to refresh array
; Initiate unlock sequence
;
;
;
; Set WR bit to begin write
; Wait for write to complete
; Increment address low byte
; Not zero, do it again
//The following 4 lines of code are not needed if the part doesn't have NVMADRH register
INCF
NVMADRH, F
; Decrement address high byte
MOVLW
0x03
; Move 0x03 to working register
CPFSGT NVMADRH
; Compare address high byte with working register
BRA
Loop
; Skip if greater than working register
; Else go back to erase loop
BCF
NVMCON1, WREN
BSF
INTCON, GIE
; Disable writes
; Enable interrupts
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 143