PIC18LF24K Datasheet, PDF (307/594 Pages) –

PIC18(L)F26/45/46K40
24.12 Operation During Sleep
The CWG module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock and input sources selected
remain active.
The HFINTOSC remains active during Sleep when all
the following conditions are met:
• CWG module is enabled
• Input source is active
• HFINTOSC is selected as the clock source,
regardless of the system clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
source, when the CWG is enabled and the input source
is active, then the CPU will go idle during Sleep, but the
HFINTOSC will remain active and the CWG will con-
tinue to operate. This will have a direct effect on the
Sleep mode current.
24.13 Configuring the CWG
1. Ensure that the TRIS control bits corresponding
to CWG outputs are set so that all are
configured as inputs, ensuring that the outputs
are inactive during setup. External hardware
should ensure that pin levels are held to safe
levels.
2. Clear the EN bit, if not already cleared.
3. Configure the MODE<2:0> bits of the
CWG1CON0 register to set the output operating
mode.
4. Configure the POLy bits of the CWG1CON1
register to set the output polarities.
5. Configure the ISM<2:0> bits of the CWG1ISM
register to select the data input source.
6. If a steering mode is selected, configure the
STRx bits to select the desired output on the
CWG outputs.
7. Configure the LSBD<1:0> and LSAC<1:0> bits
of the CWG1ASD0 register to select the auto-
shutdown output override states (this is
necessary even if not using auto-shutdown
because start-up will be from a shutdown state).
8. If auto-restart is desired, set the REN bit of
CWG1AS0.
9. If auto-shutdown is desired, configure the ASxE
bits of the CWG1AS1 register to select the shut-
down source.
10. Set the desired rising and falling dead-band
times with the CWG1DBR and CWG1DBF
registers.
11. Select the clock source in the CWG1CLKCON
register.
12. Set the EN bit to enable the module.
13. Clear the TRIS bits that correspond to the CWG
outputs to set them as outputs.
If auto-restart is to be used, set the REN bit and the
SHUTDOWN bit will be cleared automatically. Other-
wise, clear the SHUTDOWN bit in software to start the
CWG.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 307