PIC18LF24K Datasheet, PDF (350/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 26-8: SSPxCON2: MSSPx CONTROL REGISTER 2 (I²C MASTER MODE)
R/W-0
GCEN
R/W/HC-0
ACKSTAT
R/W-0
ACKDT⁽¹⁾
R/W-0
ACKEN⁽²⁾
R/W-0
RCEN⁽²⁾
R/W-0
PEN⁽²⁾
R/W-0
RSEN⁽²⁾
bit 7
R/W-0
SEN⁽²⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HC = Bit is cleared by hardware
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit
Unused in Master mode.
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)⁽¹⁾
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit⁽²⁾
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;
automatically cleared by hardware
0 = Acknowledge sequence is Idle
bit 3
RCEN: Receive Enable bit (Master Receive mode only)⁽²⁾
1 = Enables Receive mode for I²C
0 = Receive is Idle
bit 2
PEN: Stop Condition Enable bit⁽²⁾
1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Stop condition is Idle
bit 1
RSEN: Repeated Start Condition Enable bit⁽²⁾
1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Repeated Start condition is Idle
bit 0
SEN: Start Condition Enable bit⁽²⁾
1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Start condition is Idle
Note 1:
2:
The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
If the I²C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 350