PIC18LF24K Datasheet, PDF (302/594 Pages) –

PIC18(L)F26/45/46K40
24.3 Clock Source
The clock source is used to drive the dead-band timing
circuits. The CWG module allows the following clock
sources to be selected:
• FOSC (system clock)
• HFINTOSC
When the HFINTOSC is selected, the HFINTOSC will
be kept running during Sleep. Therefore, CWG modes
requiring dead band can operate in Sleep, provided
that the CWG data input is also active during Sleep.The
clock sources are selected using the CS bit of the
CWG1CLKCON register (Register 24-3). The system
clock FOSC, is disabled in Sleep and thus dead-band
control cannot be used.
24.4 Selectable Input Sources
The CWG generates the output waveforms from the
input sources in Table 24-1.
TABLE 24-1: SELECTABLE INPUT
SOURCES
Source
Peripheral
Signal Name
ISM<2:0>
CWG1PPS
Pin selected by
CWG1PPS
000
CCP1
CCP1 Output
001
CCP2
CCP2 Output
010
PWM3
PWM3 Output
011
PWM4
PWM4 Output
100
CMP1
Comparator 1 Output
101
CMP2
Comparator 2 Output
110
DSM
Data signal modulator
output
111
The input sources are selected using the ISM<2:0> bits
in the CWG1ISM register (Register 24-4).
24.5 Output Control
24.5.1 CWG OUTPUTS
Each CWG output can be routed to a Peripheral Pin
Select (PPS) output via the RxyPPS register (see Sec-
tion 17.0 “Peripheral Pin Select (PPS) Module”).
24.5.2 POLARITY CONTROL
The polarity of each CWG output can be selected inde-
pendently. When the output polarity bit is set, the corre-
sponding output is active-high. Clearing the output
polarity bit configures the corresponding output as
active-low. However, polarity does not affect the over-
ride levels. Output polarity is selected with the POLy
bits of the CWG1CON1. Auto-shutdown and steering
options are unaffected by polarity.
24.6 Dead-Band Control
The dead-band control provides non-overlapping PWM
signals to prevent shoot-through current in PWM
switches. Dead-band operation is employed for Half-
Bridge and Full-Bridge modes. The CWG contains two
6-bit dead-band counters. One is used for the rising
edge of the input source control in Half-Bridge mode or
for reverse dead-band Full-Bridge mode. The other is
used for the falling edge of the input source control in
Half-Bridge mode or for forward dead band in Full-
Bridge mode.
Dead band is timed by counting CWG clock periods
from zero up to the value in the rising or falling dead-
band counter registers. See CWG1DBR and
CWG1DBF registers, respectively.
24.6.1
DEAD-BAND FUNCTIONALITY IN
HALF-BRIDGE MODE
In Half-Bridge mode, the dead-band counters dictate
the delay between the falling edge of the normal output
and the rising edge of the inverted output. This can be
seen in Figure 24-2.
24.6.2
DEAD-BAND FUNCTIONALITY IN
FULL-BRIDGE MODE
In Full-Bridge mode, the dead-band counters are used
when undergoing a direction change. The MODE<0>
bit of the CWG1CON0 register can be set or cleared
while the CWG is running, allowing for changes from
Forward to Reverse mode. The CWG1A and CWG1C
signals will change immediately upon the first rising
input edge following a direction change, but the modu-
lated signals (CWG1B or CWG1D, depending on the
direction of the change) will experience a delay dictated
by the dead-band counters.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 302