PIC18LF24K Datasheet, PDF (252/594 Pages) –

PIC18(L)F26/45/46K40
20.6.1 SOFTWARE GATE MODE
The Software Gate mode corresponds to legacy Timer2
operation. The timer increments with each clock input
when ON = 1 and does not increment when ON = 0.
When the TMRx count equals the PRx period count the
timer resets on the next clock and continues counting
from 0. Operation with the ON bit software controlled is
illustrated in Figure 20-4. With PRx = 5, the counter
advances until TMRx = 5, and goes to zero with the next
clock.
FIGURE 20-4:
SOFTWARE GATE MODE TIMING DIAGRAM
Rev. 10-000195B
5/30/2014
MODE
0b00000
TMRx_clk
Instruction⁽¹⁾
BSF
BCF
BSF
ON
PRx
5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1
2
34501
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 252