PIC18LF24K Datasheet, PDF (38/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 4-3: OSCCON3: OSCILLATOR CONTROL REGISTER 3
R/W/HC-0/0 R/W-0/0
U-0
R-0/0
R-0/0
U-0
U-0
U-0
CSWHOLD SOSCPWR
—
ORDY
NOSCR
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
CSWHOLD: Clock Switch Hold bit
1 = Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready
0 = Clock switch may proceed when the oscillator selected by NOSC is ready; NOSCR
becomes ‘1’, the switch will occur
SOSCPWR: Secondary Oscillator Power Mode Select bit
1 = Secondary oscillator operating in High-Power mode
0 = Secondary oscillator operating in Low-Power mode
Unimplemented: Read as ‘0’
ORDY: Oscillator Ready bit (read-only)
1 = OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC
0 = A clock switch is in progress
NOSCR: New Oscillator is Ready bit (read-only)⁽¹⁾
1 = A clock switch is in progress and the oscillator selected by NOSC indicates a “ready” condition
0 = A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready
Unimplemented: Read as ‘0’
Note 1: If CSWHOLD = 0, the user may not see this bit set because, when the oscillator becomes ready there
may be a delay of one instruction clock before this bit is set. The clock switch occurs in the next instruction
cycle and this bit is cleared.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 38